A Minimal CISC Processor Architecture for Field Programmable Gate Arrays

Decreasing cost and increased complexity of modern field programmable gate array (FPGA) devices, such as Xilinx’s Spartan 3[1], have allowed the development of true system on a chip (SOC) architectures for embedded micro-controller and ubiquitous computing applications. To minimize the size and, therefore, the cost of the required FPGA, consideration must be given to matching the desired functionality to the FPGA’s resources. This paper describes the initial work in comparing software, firmware and hardware biased solutions and a reconsideration of complex instruction set computer (CISC) based processor architectures to achieve this aim. One of the main developments in FPGA design that has permitted true SOC architectures to be developed is the increasing amount of onchip memory. In general, this can be divided into two types; distributed and block RAM. Distributed RAM is implemented from lookup tables within the general purpose logic resources of the FPGA, whereas block RAM is a true dual port memory element, with configurable address and data bus widths, organized in columns throughout the FPGA. To maximise the speed and area performance of these devices and, therefore, minimize cost, consideration of these hardware resources within the FPGA must be made before a design solution is made. A typical embedded FPGA micro-controller is normally based on a RISC processor core. This processor uses block RAM for its data and instruction memory. However, its instruction decoder and control logic are constructed from general purpose logic, reducing FPGA resources that are available for peripheral devices. An alternative solution to minimise this problem is the CISC processor core. This processor again uses block RAM for its data and instruction memory and also for its control logic, as part of a microprogrammed (firmware) controller. This frees up general purpose logic, allowing more support to be included within the processor for specific applications, for peripheral devices, or simply to allow smaller, cheaper FPGAs to be used. In the 1950s Professor M.V. Wilkes first recognised that a processor’s control unit was implemented as a series of discrete steps much like an ordinary computer program [2]. This lead to the development of microprogrammed control units that are commonly found in CISC processors, where each machine instruction is interpreted by a microprogram stored in control memory within the processor. These microprograms are composed of a series of microinstructions, which themselves can be composed of a series of nanoinstructions [3] defining the control signals required to perform the desired machine operation, as shown in figure 1.